The present invention is directed to semiconductor devices and, more specifically, to thyristor-based devices such as thyristor-based memory devices and switching circuits.
Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Presently, single-die microprocessors are being manufactured with many millions of transistors, operating at speeds of hundreds of millions of instructions per second and being packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices have led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the circuit design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density has benefits including low price). DRAM cell size is typically between 6 F2 and 8 F2, where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order or magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density and exhibits a feature size that is typically between about 60 F2 and 100 F2.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. These problems include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
Thin capacitively-coupled thyristor-type NDR device can be used to overcome a variety of limitations, including those discussed above, in memory cells and other devices. However, an important consideration in semiconductor device design, including the design of memory cells employing thin capacitively-coupled thyristors, is forming the device in a highly dense array. In order to achieve a dense array, dielectric and/or insulative material is often located near to conductors carrying a voltage that can induce stress on thermally-grown oxide and other similar materials. In addition, it is sometimes difficult to thermally grow a high quality oxide dielectric on a silicon substrate having a high concentration of defects therein.
These and other design considerations have presented challenges to the implementation of such a thin capacitively-coupled thyristor to bulk substrate applications, and in particular to applications where highly-dense arrays of thyristors are desirable.
The present invention is directed to overcoming the above-mentioned challenges and others related to the types of devices and applications discussed above and in others, such as memory cells and switching circuits. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor device is manufactured with trench in a substrate, the trench being at least partially filled with both a dielectric material and a capacitively-coupled control port. The trench is formed adjacent to a thyristor body region, and control port is adapted for capacitively coupling to the thyristor body for controlling current flow therein. The dielectric material is deposited and/or thermally grown, with deposited or partially deposited dielectric material being able to withstand a higher voltage stress, for example, relative to similar thermally-grown dielectric. In one particular implementation, deposited or partially deposited dielectric material has a higher capacitive coupling ratio (e.g., between the control port and the thyristor body) than a thermally grown dielectric, under certain conditions. These approaches are particularly useful, for example, when trying to form a dielectric on silicon, such as polycrystalline silicon typically used in semiconductor substrates.
In connection with one implementation, deposited dielectric material is used in the trench, either alone or in combination with thermally-grown dielectric material. It has been discovered that the defect density of such a deposited dielectric material is relatively independent of the crystalline structure and/or defects present in silicon on which the dielectric is deposited, such as silicon on sidewalls of the trench, and/or doped silicon filler material in the trench. With this approach, it is possible to form a much higher quality dielectric (e.g., fewer defects, less susceptible to breakdown and thus more reliable) relative to, for example, dielectric formed using thermal oxidation alone.
In another implementation, highly-doped silicon (e.g., crystalline and/or polycrystalline silicon) is used in selected portions of the semiconductor device where oxide material is to be thermally grown. In one instance, doped polysilicon filler material is formed in the trench, and in another instance, silicon sidewalls of the trench are doped. Oxide material is then thermally grown with conditions that result in a much thicker oxide layer being formed on highly-doped portions of the silicon, relative to an oxide layer thermally-grown on lower-doped portions of the silicon. With this approach, relatively different oxide thicknesses in the trench can be achieved using a single thermal growth process. This approach is particularly useful, for example, when the thermally-grown oxide is to be used for different purposes in different portions of the trench, such as for electrically isolating the control port and for separating the control port from conductive material in the trench.
In another example embodiment of the present invention, a memory array includes a plurality of memory cells, each memory cell having a capacitively-coupled thyristor and one or more deposited and/or thermally-grown dielectric materials in a trench, as discussed above. Each thyristor includes anode and cathode end portions, each end portion having a base region electrically coupled to an emitter region, and each base region being electrically coupled to one another. Each memory cell also includes a pass device having source/drain regions separated by a channel region and a gate capacitively coupled to the channel region. One of the source/drain regions is coupled in series with the thyristor at a first one of the emitter regions, and another one of the source/drain regions is coupled to a bit line. A first word line is adapted to apply a voltage to the gate of the pass device for controlling the current flow therein, where the pass device forms a conductive link between the bit line and the thyristor when the pass device is in a conducting state. A second word line is adapted to apply a voltage to the control port of the thyristor for controlling current flow therein, and a second one of the emitter regions is coupled to a conductor at a reference voltage.